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SmartASIC, Inc. reserves the right to change or modify the information contained herein without notice. It is the customer's responsibility to ensure OVERVIEW he/she has the most recent revision of the user guide. SmartASIC, Inc. makes no warranty foris enhanced version of the SD1000 chip. It is an ICfor any error digital-interface The SD1010D the use of its products and bears no responsibility designed for or omissions, which may appear in this document. monitor takes digital RGB signals from a XGA TFT LCD monitors. A digital-interface LCD graphic card of a personal computer, the exact same input interface as a conventional CRT monitor. This feature makes digital-interface LCD monitor a true replacement of a conventional CRT monitor.
The digital input RGB signals are first received by TMDS receiver, and the 24-bit RGB data are then fed into the SD1010D. The SD1010D is capable of performing automatic detection of the display resolution and timing of input signals generated from various PC graphic cards. No special driver is required for the timing detection, nor any manual adjustment. The SD1010D then automatically scales the input image to fill the full screen of the LCD monitor. The SD1010D can interface with TFT LCD panels from various manufacturers by generating either 24-bit or 48-bit RGB signal to the LCD panel based upon the timing parameters saved in the EEPROM.
The SD1010D implements four advanced display technologies: 1. Advanced mode detection without any external CPU assist 2. Advanced programmable interpolation algorithm 3. Stand-alone mode support, and 4. Advanced true color support with both dithering and frame modulation. The SD1010D also provides distinguished system features to the TFT LCD monitor solution. The first one is "plug-and-play", and the second one is "cost-effective system solution". To be truly plug-and-display, the SD1010D performs automatic input mode detection. Furthermore, the SD1010D can generate output video even when the input signal is beyond the specifications or no input signal is fed. For "cost-effective system solution", the SD1010D implements many system support features such as OSD mixer, error status indicators, 2-wire serial interface for both EEPROM and host CPU interface, and low-cost IC package. Another important contributing factor is that the SD1010D does not require external frame buffer memory for the automatic image scaling and synchronization. Figure 1 shows the block diagram of the SD1010D as well as the connections of important system components around the SD1010D.
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Figure 1: SD1010D Functional Block Diagram
Input Mode Detection & TMDS
Auto Calibration
Buffer Memor y
Scaling Interpolati on Dithering OSD Mixe r E2ROM Interface TFT LCD Monitor
Write Contro l CPU Interfac e
Read Contro l
CP
Outpu t PLL
E2PRO M
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PIN DESCRIPTION
Figure 2: SD1010D package diagram
102 120 1031 21
65 81 64 80
SmartASIC SD1010D
1281 60 1 38 40
39 41
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Table 1: SD1010 pin description (sorted by pin number)
Symbol ROM_SCL ROM_SDA GND CPU_SCL CPU_SDA PWM_CTL CLK_1M VDD CLK_1M_O RESET_B R_OSD G_OSD B_OSD EN_OSD PIN Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O Description O SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface Ground I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface O PWM control signal (not used) I Free Running Clock (default: 1MHz) Power Supply O Feedback of free Running Clock I System Reset ( active LOW) I OSD Color Red I OSD Color Green I OSD Color Blue I OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times } I Manufacturing test pin (NC) I Manufacturing test pin (NC) O Input PLL Feedback Clock (not used) I Input Clock 0 (not used) O Output PLL Feedback Clock I Output PLL Output Clock O Output HSYNC (the polarity is programmable through CPU, default is active low) O Output VSYNC (the polarity is programmable through CPU, default is active low) O Output Clock to Control Panel (the polarity is programmable through CPU) O Output Display Enable for Panel (the polarity is programmable through CPU, default is active HIGH) Ground Power Supply O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) O Default HSYNC generated by ASIC (active LOW) O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) O Output Color Red Even Pixel (left pixel) Ground O Output Color Red Odd Pixel (right pixel) O Output Color Red Odd Pixel (right pixel) O Output Color Red Odd Pixel (right pixel) O Output Color Red Odd Pixel (right pixel) Power Supply O Output Color Red Odd Pixel (right pixel) O Output Color Red Odd Pixel (right pixel) O Output Color Red Odd Pixel (right pixel) 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
SCAN_EN TEST_EN FCLK0 VCLK0 FCLK1 VCLK1 HSYNC_O VSYNC_O DCLK_OUT DE_OUT GND VDD R_OUT0_E R_OUT1_E R_OUT2_E R_OUT3_E HSYNC_X R_OUT4_E R_OUT5_E R_OUT6_E R_OUT7_E GND R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O VDD R_OUT4_O R_OUT5_O R_OUT6_O
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
R_OUT7_O GND G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E G_OUT4_E VDD G_OUT5_E G_OUT6_E G_OUT7_E GND GND G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O VDD G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O GND GND B_OUT0_E B_OUT1_E B_OUT2_E B_OUT3_E B_OUT4_E B_OUT5_E B_OUT6_E VDD VDD B_OUT7_E GND B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O VDD B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O GND R_IN00 R_IN01 R_IN02 R_IN03 VDD R_IN04 R_IN05 R_IN06
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
O O O O O O O O O
Output Color Red Odd Pixel (right pixel) Ground Output Color Green Even Pixel (left pixel)
Output Color Green Even Pixel (left pixel)
Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Power Supply Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Ground Ground Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Power Supply Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Ground Ground Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Power Supply Power Supply Output Color Blue Even Pixel (left pixel) Ground Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Power Supply Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Ground Channel A Data Input Color Red (LSB) Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Power Supply Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red
O O O O O O O O
O O O O O O O
O O O O O O O O O I I I I I I I
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R_IN07 GND VDD GND G_IN00 G_IN01 G_IN02 G_IN03 VDD G_IN04 G_IN05 ADC_CLK0 G_IN06 G_IN07 GND VDD GND B_IN00 B_IN01 B_IN02 VDD B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 GND HSYNC_I VSYNC_I DE_IN VDD
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
I
I I I I I I O I I
I I I I I I I I I I I
Channel A Data Input Color Red (MSB) Ground Power Supply Ground Channel A Data Input Color Green (LSB) Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Power Supply Channel A Data Input Color Green Channel A Data Input Color Green Sample Clock for ADC 0 (not used) Channel A Data Input Color Green Channel A Data Input Color Green (MSB) Ground Power Supply Ground Channel A Data Input Color Blue (LSB) Channel A Data Input Color Blue Channel A Data Input Color Blue Power Supply Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue (MSB) Ground Input HSYNC (any polarity) Input VSYNC (any polarity) DE input for digital interface Power Supply
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Table 2: SD1010 pin description (sorted by function)
Symbol R_IN00 R_IN01 R_IN02 R_IN03 R_IN04 R_IN05 R_IN06 R_IN07 G_IN00 G_IN01 G_IN02 G_IN03 G_IN04 G_IN05 G_IN06 G_IN07 B_IN00 B_IN01 B_IN02 B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 HSYNC_I VSYNC_I DE_IN ADC_CLK0 R_OUT0_E R_OUT1_E R_OUT2_E R_OUT3_E R_OUT4_E R_OUT5_E R_OUT6_E R_OUT7_E R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O R_OUT4_O R_OUT5_O R_OUT6_O R_OUT7_O G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E PIN Number 90 91 92 93 95 96 97 98 102 103 104 105 107 108 110 111 115 116 117 119 120 121 122 123 125 126 127 109 27 28 29 30 32 33 34 35 37 38 39 40 42 43 44 45 47 48 49 50 I/O I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O Description Channel A Data Input Color Red (LSB) Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red (MSB) Channel A Data Input Color Green (LSB) Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green (MSB) Channel A Data Input Color Blue (LSB) Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue (MSB) Input HSYNC (any polarity) Input VSYNC (any polarity) DE input for digital interface Sample Clock for ADC 0 (not used) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel)
O Output Color Green Even Pixel (left pixel) O Output Color Green Even Pixel (left pixel) O Output Color Green Even Pixel (left pixel) O Output Color Green Even Pixel (left pixel) 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
G_OUT4_E G_OUT5_E G_OUT6_E G_OUT7_E G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O B_OUT0_E B_OUT1_E B_OUT2_E B_OUT3_E B_OUT4_E B_OUT5_E B_OUT6_E B_OUT7_E B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O HSYNC_O VSYNC_O DCLK_OUT DE_OUT
51 53 54 55 58 59 60 61 63 64 65 66 69 70 71 72 73 74 75 78 80 81 82 83 85 86 87 88 21 22 23 24
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output HSYNC (the polarity is programmable through CPU, default is active low) Output VSYNC (the polarity is programmable through CPU, default is active low) Output Clock to Control Panel (the polarity is programmable through CPU) Output Display Enable for Panel (the polarity is programmable through CPU, default is active HIGH) Input PLL Feedback Clock (not used) Input Clock 0 (not used) Output PLL Feedback Clock Output PLL Output Clock SCL in I2C for EEPROM interface SDA in I2C for EEPROM interface SCL in I2C for CPU interface SDA in I2C for CPU interface PWM control signal (not used) Free Running Clock (default: 1MHz) Feedback of free Running Clock
FCLK0 VCLK0 FCLK1 VCLK1 ROM_SCL ROM_SDA CPU_SCL CPU_SDA PWM_CTL CLK_1M CLK_1M_O
17 18 19 20 1 2 4 5 6 7 9
O I O I O I/O I I/O O I O
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RESET_B HSYNC_X R_OSD G_OSD B_OSD EN_OSD
10 31 11 12 13 14
I O I I I I
System Reset ( active LOW) Default HSYNC generated by ASIC (active LOW) OSD Color Red OSD Color Green OSD Color Blue OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times } Manufacturing test pin (NC) Manufacturing test pin (NC) Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
SCAN_EN TEST_EN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
15 16 8 26 41 52 62 76 77 84 94 100 106 113 118 128 3 25 36 46 56 57 67 68 79 89 99 101 112 114 124
I I
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FUNCTIONAL DESCRIPTION
The SD1010D has the following major function blocks: 1. Input mode detection 2. Buffer memory and read/write control block 3. Image scaling, interpolation and dithering block 4. OSD mixer and LCD interface block 5. EEPROM interface block 6. CPU interface block The following sections will describe the functionality of these blocks.
Input mode detection i) Supported input modes
SD1010D can handle up to 14 different input modes. For SD1010D, an input mode is defined by its horizontal resolution with its vertical resolution. The input modes with the same horizontal and vertical resolution but with different frame rates are still considered as one single input mode. In the default EEPROM setup, SD1010D accepts the following seven input video modes: 1. 2. 3. 4. 5. 6. 7. 640 x 350 640 x 400 720 x 400 640 x 480 (VGA) 800 x 600 (SVGA) 832 x 624 (MAC) 1024 x 768 (XGA)
Users can easily change the definitions of the acceptable input modes by adjusting the values in the appropriate EEPROM entries. There is no frame rate restriction on the input modes. However, since the output signal is synchronized with the input signal at the same refresh rate, the input refresh rate has to be within the acceptable range of the LCD panel. The user-defined video modes can be defined by storing appropriate timing information in the EEPROM. Detail definitions of the EEPROM entries are described in Section 3.5.2.
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ii)
Input mode detection
The SD1010D can automatically detect the mode of the input signal without any user adjustment or driver running on the PC host or external CPU. This block automatically detects polarity of input synchronization and the sizes of back porch, valid data window and the synchronization pulse width in both vertical and horizontal directions. The size information is then used not only to decide the input resolution, to lock the PLL output clock with HSYNC, but also to automatically scale the image to full screen and to synchronize the output signal with the input signal. The detection logic is always active to automatically detect any changes to the input mode. Users can manually change the input mode information at run time through the CPU interface. Detailed operation of the CPU interface is described in Section 3.6. "CPU Interface". Mode detection can be independently turned ON or OFF by the external CPU. This feature allows system customers to have better control of the mode-detection process. When the detection is turned OFF, the external CPU can change the input mode.
iii) Free Running Clock
As described in previous section, a free-running clock is needed for the SD1010D. This clock is used for many of the SD1010D's internal operations. Eeprom operation is one of them. System manufacturers can select the frequency of the free-running clock, and the default clock frequency is 1MHz. System manufacturers can use an oscillator to generate the free-running clock, and feed that clock directly to the pin "CLK_1M", or use a crystal connecting to "CLK_1M" and "CLK_1M_O".
Buffer memory and read/write control block
The SD1010D uses internal buffer memory to store a portion of the input image for image scaling and output synchronization. No external memory buffer is needed for the SD1010D. The write control logic ensures the input data are stored into the right area of the buffer memory, and the read control logic is responsible to fetch the data from the buffer memory from the correct area and at the correct timing sequence. With the precise timing control of the write and read logic, the output image is appropriately scaled to the full screen, and the output signal is perfectly synchronized with the input signals.
Image scaling, interpolation and dithering block
The SD1010D supports both automatic image scaling and interpolation.
iv) Image scaling
The SD1010D supports several different input modes, and the input image may have different sizes. It is essential to support automatic image scaling so that the input image is always
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displayed to the full screen regardless the input mode. The SD1010D scales the images in both horizontal and vertical directions. It calculates the correct scaling ratio for both directions based upon the LCD panel resolution and the input mode and timing information produced by the "Input mode detection" block. The scaling ratio is re-adjusted whenever a different input mode is detected. The ratio is then fed to the buffer memory read control logic to fetch the image data with the right sequence and timing. Some of the image data may be read more than once to achieve the scaling effect.
v) Image interpolation
The SD1010D supports image interpolation to achieve better image quality. A basic image scaling algorithm replicates the input images to achieve the scaling effect. The replication scheme usually results in a poor image quality. The SD1010D implements a proprietary interpolation algorithm to improve the image quality. The programmable interpolation is implemented with a 256-entry mapping table in the EEPROM to allow system users to adjust the bi-linear interpolation parameters to control the sharpness and smoothness quality of the image. In the default setting, the mapping table contains a straight line of slope equal to 1, i.e. the data in entry N equal to the value N. If the mapping table contains a line of slope equal to 2, then the output image will be a bit sharper than the image generated by a table with the default setting. Through an external microcontroller, users can chose among different interpolation algorithm.
vi) Dithering
The SD1010D supports 16.7 million true colors for a 6-bit panel. Two dithering algorithms are implemented and users can chose between them through the external microcontroller. The first one is area-based dithering, and the second one is a frame-based frame modulation, which also is called frame rate control. Through the external microcontroller, users can choose among different dithering algorithms.
vii)
Text Enhancement
In order to generate a good picture, the SD1010D incorporate a proprietary scheme to detect text and non-text picture. Then applying the appropriate process to improve the text image based on the detection of incoming source. By using the text enhancement function correctly, the text image will look more pleasant and near perfect after scaled up or down. Users can achieve a preferred image by changing the settings in "text control" register.
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viii)
Sharpness Enhancement
No matter how many times the original image got enlarged or shrunk by the internal interpolator. With the embedded powerful DSP arrays, SD1010D always can enhance the overall image sharpness (edge) to different degree for the various requirements. The sharpness can be adjusted bi-directionally which means either going sharper or softer to certain point set by the user. It's easy to activate the sharpness enhancement by program "sharpness control" register.
OSD mixer and LCD interface
At the output stage, the SD1010D performs the OSD mixer function, and then generates the 24bit / 48-bit RGB signal to the LCD panel with the correct timing.
ix) OSD mixer
In the OSD mixer block, the SD1010D mixes the normal output RGB signal with the OSD signal. The OSD output data is generated based on the "R_OSD", "G_OSD" and "B_OSD" pins as well as the "OSD Intensity" data in EEPROM entry. When the "EN_OSD" is active high, the OSD is active, and the SD1010D will send the OSD data to the LCD panel. The OSD has 16 different color schemes based on the combinations of the three OSD color pins and the "OSD Intensity" data. When R_OSD=1, and OSD_Intensity=0, the SD1010D will output 128 to the output red channel, R_OUT. When R_OSD=1 and OSD_Intensity=1, the SD1010D will output 255. The same scheme is used for G_OSD to G_OUT and for B_OSD to B_OUT. As part of the mixer control function, the SD1010D implements three mixing control registers, "OSD R Weight" (38H), "OSD G Weight"(39H), and "OSD B Weight" (3AH). The mixing equation is shown below:
R_OUT = (R_OSD) * (OSD R Weight/255) + R * (1 - OSD R Weight/255) G_OUT = (G_OSD) * (OSD G Weight/255) + G * (1 - OSD G Weight/255) B_OUT = (B_OSD) * (OSD B Weight/255) + B * (1 - OSD B Weight/255)
When the weight is 255, the OSD output will overlay on top of the normal output. When the weight is 0, the OSD output is disabled.
x) LCD interface
The SD1010D support both 24- and 48-bit RGB interfaces with XGA LCD panels from various panel manufacturers. The LCD panel resolution and timing information is stored in the external EEPROM. The information in the EEPROM includes timing related to the output back porch,
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synchronization pulse width and valid data window. The timing information is used to generate the frequency divider for the output PLL, to lock the PLL output clock with HSYNC for the LCD data clock, and to synchronize the output VSYNC and input VSYNC.
EEPROM interface
As mentioned in previous sections, the external EEPROM stores crucial information for the SD1010D internal operations. The SD1010D interfaces with the EEPROM through a 2-wire serial interface. The suggested EEPROM device is an industry standard serial-interface EEPROM (24x08). The 2-wire serial interface scheme is briefly described here and a detailed description can be found in public literature.
xi) 2-wire serial interface
The 2-wire serial interface uses 2 wires, SCL and SDA. The SCL is driven by the SD1010D and used mainly as the sampling clock. The SDA is a bi-directional signal and used mainly as a data signal. Figure 4 shows the basic bit definitions of the 2-wire serial interface. The 2-wire serial interface supports random and sequential read operations. Figures 5 and 6 show the data sequences for random read and sequential read operations.
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Figure 4: START, STOP AND DATA Definitions in 2-wire serial interface
SDA
SCL
DATA STABLE
START
DATA CHANGE
DATA CHANGE
STOP
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Figure 5: Data sequence for read access (both single and multiple bytes)
R EA AC DK W R I T S AT CO KP
EVICE DDRESS
:0]
WORD ADDRESS [5:0]
A C K
S T O P
S TT O A PR T
DUMMY READDE VICE
RA EC AK D R E A D
DATA READ
L SR B /_ W B I T 0
M S B B I T
M S B B I T
L S B B I T 0
M S B B I T
L S B B I T 0
7
7 6
7
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Figure 6: Data sequence for write access (both single and multiple bytes)
W RA IC TK ER E A D S T A O C P K
DEVICE ADDRESS
[6:0]
WORD ADDRESS [5:0]
A C K
DATA n
A C K
DATA n+x
L R S /_ B W B I T 0
M S B B I T
M S B B I T
L S B B I T 0
M S B B I T
L S B B I T 0
7
7
7
xii)
EEPROM Contents
The contents of EEPROM are primarily dependent on the specifications of the LCD panel. SmartASIC provides suggested EEPROM contents for LCD panels from various panel manufacturers. The section presents all the entries in the EEPROM, and briefly describes their definitions. This allows the system manufacturers to have their own EEPROM contents to distinguish their monitors. The EEPROM contents can be partitioned into 16 parts. The first 14 parts are input mode dependent. When the SD1010D detects the input mode, it will then load the information related to the detected mode from the EEPROM. The information in the 15th part is mainly for input mode detection as well as some threshold values for error status indicators. The 16th part is the look up table for the gamma correction function. The 15th and 16th part are loaded in the SD1010D during the reset time. In the default setting, the SD1010D is set to recognize the following seven modes: 640x350, 640x400, 720x400, 640x480, 800x600, 832x624, and 1024x768 modes. Then the EEPROM will be partitioned as follows:
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* * * * * * * * * * * * * * * *
Part 1: mode 1: 640x350 mode (in default setting) Part 2: mode 2: 640x400 mode (in default setting) Part 3: mode 3: 720x400 mode (in default setting) Part 4: mode 4: 640x480 mode (in default setting) Part 5: mode 5: 800x600 mode (in default setting) Part 6: mode 6: 832x624 mode (in default setting) Part 7: mode 7: 1024x768 mode (in default setting) Part 8: mode 8 Part 9: mode 9 Part 10: mode 10 Part 11: mode 11 Part 12: mode 12 Part 13: mode 13 Part 14: mode 14 Part 15: input mode detection and scaling related parameters Part 16: look up table for gamma correction
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Part 1-14: Input Mode Dependent Data
Symbol Width (bits) 11 11 11 11 11 11 11 11 11 12 4 Address For 640x350 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H [6:3] Description
VPW VBP VBP Source Target Skip Pixel VSIZE HPW HBP HSIZE HTOTAL HTOTAL Source Line Expansion Pixel Expansion H. Fog Factor H. Fog Factor V. Fog Factor V. Fog Factor Minimum Input lines [10:8] Maximum Input pixels [10:8] Minimum input lines [7:0]
LCD VSYNC pulse width LCD VSYNC back porch (including VPW) LCD VSYNC back porch (source equivalent) = VBP * Line Expansion and round up If VBP can not be converted into source evenly, the leftover is converted into number of pixels LCD number of lines LCD HSYNC pulse width LCD HSYNC back porch (including HPW) LCD number of columns LCD total number of pixels per line including all porches LCD total number of clocks per line (source equivalent) = HTOTAL/Line Expansion Vertical source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-15: expansion ratio other than one-to-one (expansion) Horizontal source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-7: expansion ratio other than one-to-one (expansion) Horizontal fogging factor high byte Horizontal fogging factor low byte Vertical fogging factor high byte Vertical fogging factor low byte Upper 3 bits of minimum input lines Upper 3 bits of maximum input pixels Minimum input lines = (VSIZE + VBP)* Line Expansion When the input has fewer lines than this value, it is considered as an ERROR, and INPUT_X status bit will be HIGH. Maximum input pixels per line. Auto clock recovery will not set input PLL divisor larger than this value. Source horizontal size upper 3 bits Source vertical size upper 3 bits Source horizontal size lower 8 bits
3
14H [2:0]
8 8 8 8 3
15H[7:0] 16H[7:0] 17H[7:0] 18H[7:0] 19H[6:4]
3 8
19H[2:0] 1AH
Maximum input pixels [7:0] Source HSIZE[10:8] Source VSIZE[10:8] Source HSIZE[7:0]
8
1BH
3 3 8
1CH [6:4] 1CH [2:0] 1DH
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Source VSIZE[7:0] Check sum
8 8
1EH 1FH
Source vertical size lower 8 bits Sum of above 31 bytes (keep lower 8 bits only)
Mode 640x400 720x400 640x480 800x600 832x624 1024x768 User define Mode 1 User define Mode 2 User define Mode 3 User define Mode 4 User define Mode 5 User define Mode 6 User define Mode 7
Address Range 20H 3FH 40H
5FH
60H 7FH 80H
9FH
A0H BFH C0H
DFH
E0H FFH 100H 11FH 120H 13FH 140H 15FH 160H 17FH 180H 19FH 1A0H 1BFH
Part 15: Input Mode Detection Data
Symbol Control byte 0 Width (bits) 8 Address 200H Description Bit 6 - bit 0 : device ID for external CPU access Bit 7: 0: load only 1 table for RGB gamma correction 1: load three separate tables for RGB gamma correction Bit0: 0: disable automatic input gain control 1: enable automatic input gain control Bit1: 0: enable input H/V SYNC polarity control (make input SYNC positive polarity)
Control byte 1
8
201H
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Control byte 2
8
202H
1: bypass input H/V SYNC polarity control Bit2: 0: single pixel input 1: dual pixel input (set at 0) Bit3: 0: disable digital input 1: enable digital input (set at 1) Bit4: 0: YUV input format is unsigned (128 offset) 1: YUV input format is signed Bit5: 0: RGB input for video mode 1: YUV input for video mode Bit6: 0: disable video input 1: enable video input Bit7: 0: disable decimation support 1: enable decimation Bit 0: 0: don't invert input odd/even field indicator 1: invert input odd/even field indicator Bit 1: 0: disable half clock mode for dual pixel input 1: enable half clock mode for dual pixel input (set at 0) Bit 2: 0: disable BY2 for auto calibration 1: enable BY 2 for auto calibration Bit 3: 0: disable BY4 for auto calibration 1: enable BY 4 for auto calibration Bit 4: 0: disable BY8 for auto calibration 1: enable BY 8 for auto calibration Bit7-5: output clock phase adjustment, larger number gives larger phase delay.
Reserved Entries Maximum VBP Mode0 vertical size Mode1 vertical size Mode2 vertical size Mode3 vertical size Mode4 vertical size Mode5 vertical size Mode6 vertical size Mode7 vertical size Mode8 vertical size Mode9 vertical size Mode10 vertical size Mode11 vertical size Mode12 vertical size Mode0 horizontal size Mode1 horizontal size Mode2 horizontal size Mode3 horizontal size Mode4 horizontal size Mode5 horizontal size Mode6 horizontal size Mode7 horizontal size Mode8 horizontal size Mode9 horizontal size Mode10 horizontal size Mode11 horizontal size Mode12 horizontal size Reserved Reserved
8 8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 8 8
203H-220H Set to all 0 or all 1 (not used) 221H The maximum vertical back porch for input video 222H-223H Mode0 vertical size for digital input 224H-225H Mode1 vertical size for digital input 226H-227H Mode2 vertical size for digital input 228H-229H Mode3 vertical size for digital input 22AH-22BH Mode4 vertical size for digital input 22CH-22DH Mode5 vertical size for digital input 22EH-22FH Mode6 vertical size for digital input 230H-231H Mode7 vertical size for digital input 232H-233H Mode8 vertical size for digital input 234H-235H Mode9 vertical size for digital input 236H-237H Mode10 vertical size for digital input 238H-239H Mode11 vertical size for digital input 23AH-23BH Mode12 vertical size for digital input 23CH-23DH Mode0 horizontal size upper bound for digital input 23EH-23FH Mode1 horizontal size upper bound for digital input 240H-241H Mode2 horizontal size upper bound for digital input 242H-243H Mode3 horizontal size upper bound for digital input 244H-245H Mode4 horizontal size upper bound for digital input 246H-247H Mode5 horizontal size upper bound for digital input 248H-249H Mode6 horizontal size upper bound for digital input 24AH-24BH Mode7 horizontal size upper bound for digital input 24CH-24DH Mode8 horizontal size upper bound for digital input 24EH-24FH Mode9 horizontal size upper bound for digital input 250H-251H Mode10 horizontal size upper bound for digital input 252H-253H Mode11 horizontal size upper bound for digital input 254H-255H Mode12 horizontal size upper bound for digital input 256H 257H 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
Reserved Calibration mode
8 2
PWM unit delay
16
Maximum link off time
22
Maximum refresh rate
16
Maximum input frequency
8
Minimum pixels per line for LCD Switching options
11 1
258H 259H [1:0] Selects different operation modes of internal phase calibration. The selection criterion is as follows: (This entry is not used) 0: when input video signal has large overshot, it results in longest calibration time 1: when input video signal has median overshot, it results in long calibration time 2: when input video signal has normal overshot, it results in normal calibration time (recommended) 3: when input video signal has no overshot, it results in shortest calibration time 25AH-25BH The unit delay used in the external PWM delay circuitry. If the free-running clock is 1MHz, and the intended unit delay is 0.2 ns (= 5,000MHz), then a value of 5,000MHz/1MHz = 5,000 is used here. (This entry is not used) 25CH-25EH Maximum time when input HSYNC is off before the LINK_DWN pin turns ON (unit: clock period of the free running clock). If the free-running clock is 1MHz, and the intended maximum time is 1 second, then a value of 1,000,000 s/ 1 s = 1,000,000 is used here. 25FH-260H Maximum refresh rate supported by the LCD panel. If the intended maximum refresh rate is 75Hz, and the free-running clock is 1MHz, then a value of 1000000/75=133,333 is used here 261H Maximum source clock rate supported by the SD1010 (unit: frequency of free-running clock). If the intended maximum clock rate is 60MHz, and the free-running clock is 1MHz, then a value of 60 is used here. If the input signal has a higher frequency than this value, the VCLK0_X status bit will turn ON. 262H-263H Minimum number of pixels per line for LCD panel 264H[4] Enable for switching to standalone hsync and vsync during no input conditions: Default is 1 1: cpu controls the switching 0: SD1010D controls the switching.
LCD polarity
4
264H[3:0]
Controls the polarity of output VSYNC, HSYNC, clock and display enable:Bit0: 0:
clock active high, 1: clock active low Bit1: 0: HSYNC active low, 1: HSYNC active high Bit2: 0: VSYNC active low, 1: VSYNC active high Bit4: 0: de active high, 1: de active low Enable for programmable output pad: 1: output is enabled 0: output is tri-state
Output enable for output in 51-54, 56-59, 61-64, 6-69, 71-74, 76-79, 814, 86-89, 91-97, 99, 01-104, 106-109 Driving capability ontrol for output pin 1-54, 56-59, 61-64, 669, 71-74, 76-79, 81-84, 6-89, 91-97, 99, 10104, 106-109
1
265H[3]
3
265H[2:0] 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
Output enable for output in 49 (DE) Driving capability ontrol for output pin 49 DE)
1
266H[7]
3
266H[6:4]
Output enable for output in 46 (HSYNC_O) Driving capability ontrol for output pin 46 HSYNC_O)
1
266H[3]
3
266H[2:0]
Output enable for output in 49 (VSYNC_O) Driving capability ontrol for output pin 49 VSYNC_O)
1
267H[7]
3
267H[6:4]
Output enable for output in 46 (DCLK_OUT) Driving capability ontrol for output pin 46 DCLK_OUT)
1
267H[3]
3
267H[2:0]
Extension right
4
268H[7:4]
Extension left
4
268H[3:0]
Extension down
2
269H[1:0]
Check sum
8
26AH
6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Numbers of pixels extended right for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification Numbers of pixels extended left for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification Numbers of lines extended down for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification Sum of all above bytes (keep only lower 8 bit)
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Part 16: Gamma Correction Lookup Table
Symbol Mapped value Width (bits) 8 Address Description
Check sum Mapped value Check sum Mapped value Check sum
8 8 8 8 8
2C0H-3BFH This is the lookup table for the gamma correction function If 200H[7] = 0, the mapped value is used for all RGB If 200H[7] = 1, the mapped value is used only for R 3C0H Sum of above 256 bytes (keep only lower 8 bit) 420H-51FH This is the lookup table for the gamma correction function for green. This is needed only if 200H[7]=1 520H Sum of above 256 bytes (keep only lower 8 bits) 5A0H-69FH This is the lookup table for the gamma correction function for blue. This is needed only if 200H[7] = 1 6A0H Sum of above 256 bytes (keep only lower 8 bits)
CPU interface The SD1010D supports a 2-wire serial interface to an external CPU. The interface allows the external CPU to access and modify control registers inside the SD1010D. The 2-wire serial interface is similar to the EEPROM interface, and the CPU is the host that drives the SCL all the time as the clock and for "start" and "stop" bits. The SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This interface supports random and sequential write operations for the CPU to modify one or multiple control registers, and random and sequential read operations for the CPU to read all or part of the control registers. The default device ID for the SD1010D is fixed "1111111". The device ID can be programmed through EEPROM entry 200H bit 0 through bit 6. This avoids any conflict with other 2-wire serial devices on the same bus. The following table briefly describes the SD1010D control registers. The external CPU can read these registers to know the state of the SD1010D as well as the result of input mode detection and phase calibration. The external CPU can modify these control registers to disable several SD1010D features and force the SD1010D into a particular state. When the CPU modifies the control registers, the new data will be first stored in a set of shadow registers, and then copied into the actual control registers when the "CPU Control Enable" bit is set. When the "CPU Control Enable" bit is set, the external CPU will retain control and the SD1010D will not perform the auto mode detection and auto calibration. The external CPU is able to adjust the size of the output image and move the output image up and down by simply changing the porch size and pixel and line numbers of the input signal. These adjustments can be tied to the external user control button on the monitor. A set of four control registers are used to generate output signal when there is no input signal available to the SD1010D or the input signal is beyond the acceptable ranges. This operation mode is called standalone mode, which is very important for the end users when they accidentally select an input mode beyond the acceptable range of the SD1010D or when the input cable connection becomes loose for any reason. System manufacturers can display appropriate OSD warning messages on the LCD panel to notify the users about the problem.
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Table 3: SD1010 Control Registers
Symbol VBP Source VSIZE Source VTOTAL Source HBP Source HSIZE Source HTOTAL Source Mode Source Width 11 11 11 11 11 11 4 Mode RW RW RW RW RW RW RW Description Input VSYNC back porch (not include pulse width) Input image lines per frame Input total number of lines including porches Input HSYNC back porch (not include pulse width) Input image pixels per line Input total number of pixels per line including porches Input video format 0: 640x350 1: 640x400 2: 720x400 3: 640x480 4: 800x600 5: 832x624 6: 1024x768 7: user defined mode 1 8: user defined mode 2 9: user defined mode 3 10: user defined mode 4 11: user defined mode 5 12: user defined mode 6 13: user defined mode 7 14-15: error RW DH-EH Input sampling clock phase RW FH-10H For standalone mode, the pulse width of VSYNC RW 11H-12H For standalone mode, total number of line per frame RW 13H-14H For standalone mode, HSYNC active time in s RW 15H-16H For standalone mode, HSYNC cycle time in s RW 17H-26H Can be set to all 0 or all 1 (not used) RW 27H[7] Bypass Input SYNC polarity detection (default 0): 1: bypass input SYNC polarity detection 0: detect input SYNC polarity and make them negative polarity RW 28H[7] Enable dithering for 6-bit panel (default 0): 1: enable dithering 0: disable dithering *also check register Control_C[6] RW 28H[6] Enable frame modulation for 6-bit panel (default 0): 1: enable frame modulation 0: disable frame modulation *also check register Control_B[5] and Control_B[7] RW 28H[5] Enable horizontal interpolation (default 0): 1: enable horizontal interpolation 0: disable horizontal interpolation RW 28H[4] Enable vertical interpolation (default 0): 1: enable vertical interpolation 0: disable vertical interpolation RW 28H[3] Enable horizontal rounding (default 0): 1: enable horizontal rounding 0: disable horizontal rounding RW 28H[2] Enable vertical rounding (default 0): 1: enable vertical rounding 0: disable vertical rounding RW 28H[1] Enable horizontal Table Lookup (default 0): 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099 Address 0H-1H 2H-3H 4H-5H 6H-7H 8H-9H AH-BH CH[3:0]
Clock Phase Source VPW standalone VTOTAL standalone HPW standalone HTOTAL standalone Reserved Entries Bypass Sync Polarity
10 11 11 11 11 8 1
Dithering Enable
1
Frame Modulation Enable
1
Horizontal Interpolation Enable Vertical Interpolation Enable Horizontal Rounding Enable Vertical Rounding Enable Horizontal Table
1
1
1
1
1
Lookup Enable Vertical Table Lookup Enable HSYNC Threshold Enable 1 RW
1
RW
OSD Intensity
1
RW
Load ALL EEPROM Load Mode Dependent EEPROM CPU control enable
1 1
RW RW
1
RW
Status 0
8
R
Status 1
4
R
Control_A
8
RW
1: enable horizontal Table Lookup 0: disable horizontal Table Lookup 28H[0] Enable vertical Table Lookup (default 0): 1: enable vertical Table Lookup 0: disable vertical Table Lookup 29H[4] Enable detection of short lines (IBM panel only, default 0): 1: Enable such detection 0: disable such detection 29H[3] OSD intensity selection: 0: half intensity 1: full intensity 29H[2] Should be kept low most of the time. A high pulse will force SD1010 to reload all EEPROM entries 29H[1] Should be kept low most of the time. A high pulse will force SD1010 to reload mode dependent EEPROM entries 29H[0] External CPU control enable: 0: disable external CPU control. SD1010 can write control registers, but CPU only read control registers. 1: enable external CPU control. CPU can read/write control registers. SD1010 cannot write control registers 2AH Read only internal status registers: 1: indicate error status 0: indicate normal status Bit 0: EEPROM gamma correction table loading Bit 1: EERPOM gamma correction table loading Bit 2: EEPROM mode dependent entries loading Bit 3: EEPROM calibration entries loading Bit 4: input has too few lines Bit 5: no input video Bit 6: input data clock is too fast Bit 7: refresh rate exceed LCD panel specification 2BH[3:0] Internal auto calibration state 0: Idle State 1-4: Loading EEPROM data 5-9: Frequency Calibration State (Auto Frequency Calibration will be done after state 9) 10: Phase Calibration State (Auto Phase Calibration will be done after state 10) 11: Adjust Horizontal Back Porch state 12: Phase Tracking state 2CH[7:0] Control Register A: 0 - disable 1 - enable default is 00H Bit 0: Horizontal Interpolation Offset Enable Bit 1: Vertical Interpolation Offset Enable Bit 2: Horizontal Interpolation Fraction Reset Enable Bit 3: Vertical Interpolation Fraction Reset Enable Bit 4: Horizontal Interpolation Integer Increment Enable Bit 5: Vertical Interpolation Integer Increment Enable Bit 6: Single Pixel Output Mode Enable Bit 7: Disable "DE_OUT", for blanking screen purpose 2DH[7:0] Control Register B
Control_B
8
RW
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Bit [2:0]: Pixel Comparison Mode: 0: compare r even(default) 1: compare g even 2: compare b even 3: invalid 4: compare r odd 5: compare g odd 6: compare b odd 7: invalid *Using pixel comparison should program register "Pixel Comparison Value" and check register "Status 2[1:0]" Bit [4:3]: Brightness Control: 0: disable brightness control(default) 1: reduce brightness 2: increase brightness 3: invalid *Using brightness control should specify register "Brightness Adjustment" and check register "Status 2[2]" Bit [5]: Frame Modulation Mode: 0: 2-bit mode(default) 1: 1-bit mode Bit [6]: 6-bit Panel Rounding Enable: 0: disable(default) 1: enable Bit [7]: Frame Modulation Scheme Selection: 0: Scheme A(default) 1: Scheme B 2EH[7:0] Control Register C Bit [1:0]: Horizontal Interpolation Special Processing Mode: 0: disable 1: linear 2: replication(default) 3: invalid Bit [3:2]: Vertical Interpolation Special Processing Mode: 0: disable 1: linear 2: replication(default) 3: invalid Bit [4]: OSD Transparency Enable: 0: disable(default) 1: enable *also need to program registers "OSD R Weight", "OSD G Weight" and "OSD B Weight" Bit [5]: Advanced Post Processing Enable: 0: disable(default) 1: enable 525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
Control_C
8
RW
*also need to specify registers "Advanced Processing R Weight", "Advanced Processing G Weight", "Advanced Processing B Weight" , "Advanced Processing R Value", "Advanced Processing G Value" and "Advanced Processing B Value" for properly functioning Bit [6]: Dithering Scheme Selection 0: Scheme A(default) 1: Scheme B Bit [7]: Reserved 2FH[7:0] Control Register D Bit [3:0]: Advanced Processing Shift Amount. From 0 - 8. 8 is the default value. Bit [4]: Advance Mixing Shift Enable 0: disable(default) 1: enable *This is a option for Advanced Post Processing Bit [5]: OSD mode 0: Dual osd pixel mode 1: Single osd pixel mode Bit[6]: OSD pixel swaping enable 0: disable 1: enable (only valid in single osd pixel mode) Bit [7]: Reserved 30H[7:0] High Byte For Interpolation Horizontal Offset Default is 00H 31H[7:0] Low Byte For Interpolation Horizontal Offset Default is 00H 32H{7:0] High Byte For Interpolation Vertical Offset Default is 00H 33H[7:0] Low Byte For Interpolation Vertical Offset Default is 00H 34H[7:0] Bit [2:0]: High Bits For Horizontal Interpolation Reset Count. Default is 0H. Bit [7:3]: Reserved 35H[7:0] Low Byte For Horizontal Interpolation Reset Count. Default is 00H. 36H[7:0] Bit [1:0]: High Bits For Vertical Interpolation Reset Count. Default is 0H. 37H[7:0] Low Byte For Interpolation Vertical Reset Count. Default is 00H. 38H[7:0] Mixing Weight For OSD R. Default is 00H. 39H[7:0] Mixing Weight For OSD G. Default is 00H. 3AH[7:0] Mixing Weight For OSD B. Default is 00H. 3BH[7:0] Weight For Advanced Post Processing R default is 00H 3CH[7:0] Weight For Advanced Post Processing G Default is 00H 3DH[7:0] Weight For Advanced Post Processing B Default is 00H 3EH[7:0] Value For Advanced Post Processing R
Control_D
8
RW
Interpolation H. Offset Interpolation H. Offset Interpolation V. Offset Interpolation V. Offset H. Interpolation Rest Count H. Interpolation Reset Count V. Interpolation Reset Count V. Interpolation Reset Count OSD R Weight OSD G Weight OSD B Weight Advanced Processing R Weight Advanced Processing G Weight Advanced Processing B Weight Advanced Processing
8 8 8 8 8
RW RW RW RW RW
8 8 8 8 8 8 8 8 8 8
RW RW RW RW RW RW RW RW RW RW
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R Value Advanced Processing G Value Advanced Processing B Value Brightness Adjustment Pixel Comparison Value Status 2
8 8 8 8 8
RW RW RW RW R
3FH[7:0] 40H[7:0] 41H[7:0] 42H[7:0] 43H[7:0]
Default is 00H Value For Advanced Post Processing G Default is 00H Value For Advanced Post Processing B Default is 00H The Adjust Amount For Reducing/Increasing Brightness. Default is 00H. The Value To Compare The Incoming Pixel Data. Default is 00H. The Status Register 2 Bit [1:0]: Result for comparing the selected incoming pixel with "Pixel Comparison Value": 0: invalid 1: incoming pixel > "Pixel Comparison Value" 2: incoming pixel = "Pixel Comparison Value" 3: incoming pixel < "Pixel Comparison Value" Bit [2]: Status for brightness control 0: Normal, no underflow/overflow 1: brightness reduced too much causes underflow/increased too much causes overflow Bit [7:3]: Reserved Clock Recovery Control Register: Default value is 71H Bit 0: clock frequency is divisible by 2 Bit 1: clock frequency is divisible by 4 Bit 2: clock frequency is divisible by 8 Bit 3: enable phase tracking feature Bit 4: enable auto phase calibration Bit 5: enable auto frequency calibration Bit 6: enable auto mode detection Bit 7: enable operation at half clock speed (not used) Offset value added to the calibrated phase when phase tracking occurs Number of frames waited before phase tracking occurs 0: Normal phase calibration (default) 1: Final phase = phase total - phase offset 0: Disable auto phase total calculation 1: Enable auto phase total calculation (default) 0: Uses the external incoming SYNC signals (default) 1: Allow the use of the default SYNC signals instead of the incoming SYNC signals 0: Analog interface 1: Digital interface (no auto calibration) should be set at 1 Offset value subtracted from phase total when doing quick phase calculation User defined value for a particular frequency Indicates when hsize value is ready for cpu to read in man_freq_state. Read only Indicates when image quality is ready for cpu to read in man_phase_state. Read only
Recovery Control
8
RW
44H
Phase Range Phase Track Waiting Time Quick Phase Enable PWM Enable Standalone Enable
4 24 1 1 1
RW RW RW RW RW
45H 46H 48H 49H[0] 49H[1] 49H[2]
Digital Enable
1
RW
49H[3]
Phase Offset Phase Total Man_hsize_valid Man_iq_valid
10 10 1 1
RW RW R R
4AH 4BH 4CH 4DH 4EH[4] 4EH[3]
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Auto_iq_valid Divisor_valid Non_full_screen Href_reg Vref_reg Text Control
1 1 1 8 16 8
R R R R R RW
Indicates when image quality is ready for cpu to read in auto calibrate mode. Read only 4EH[1] Indicates when auto clock frequency calibration is done and frequency value is ready for cpu to read. Read only 4EH[0] Indicates when input data is non full screen. Read only 4FH This reg reports the period of hsync by counting the number of free clock cycle in one single hsync period. 50H-51H This reg reports the period of vsync by counting the number of free clock cycle in one single vsync period. 52H[7:0] Text-Enhancement Control Bit[0]: text enhancement enable 0: disable 1: enable Bit[1]: Reserved Bit[6:2]: text-enhanced level Level 0 - 14. Level "0" is the same as original source, and "14" is the highest enhancement level. Bit[7]: Reserved Default is 00H 53H[7:0] Sharpness-Enhancement Control Bit[0]: sharpness enhancement enable 0: disable 1: enable Bit[1]: Reserved Bit[6:2]: sharpness-enhanced level Level 1 - 19. Level "5" is the same as the original source. From "4" to "1" intend to soften the picture, and "1" is the softest level. From level "6" to "19" will sharpen the picture gradually. Level "19" is the sharpest output. Bit[7]: Reserved Default is 14H 54H[7:0] Control Register E Bit[3:0]: text enhancement threshold. Bit[4]: reserved Bit[6:5]: Frame Modulation Mode 0: compatible with SD1010 1-3: new schemes Bit[7]: reserved Default is 05H 55H[10:8] The x location for reading "Pixel_out" register 56H[7:0] 57H[10:8] The y location for reading "Pixel_out" register
4EH[2]
Sharpness Control
8
RW
Control_E
8
RW
Pixel_h Pixel_v
11 11
RW RW
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Pixle_out Vbp_asic_update_en Sel_ext_sync Fc3_start Channel_select
24 1 1 1 1
R RW RW RW RW
Dual_pixel
1
RW
Soft_start Man_phase_state Hsize_by842_en
1 1 1
RW RW RW
Video_mode Input_yuv Yuv_signed decimation
1 1 1 1
RW RW RW RW
Detect_en
2
RW
Agc_en Agc_gain_red Agc_gain_green Agc_gain_blue Agc_offset_red Agc_offset_green Agc_offset_blue Input_max Input_min Man_freq_state Clear_man_hsize_ valid Clear_man_iq_valid Clear_iq_valid Clear_divisor_valid Clear_nonfullscreen Divisor_value IQ_value
1 8 8 8 8 8 8 8 8 1 1 1 1 1 1 11 30
RW RW RW RW RW RW RW R R RW RW RW RW RW RW R R
58H[7:0] 59H, 5AH, Read out pixel located by "Pixel_h" and "Pixel_v" 5BH 5CH[6] Enables SD1010D to update its internal vbp value. Default is high 5CH[5] Select external hsync and vsync. 5CH[4] Forces auto calibration to recalculate h back porch Set at 0 (not used) 5CH[3] Only for single pixel input 0: takes input data from channel 1 1: takes input data from channel 0 For 128 pin package set this bit at 0 5CH[2] 0: takes input data from one single channel 1: takes input data from both channels For 128 pin package set this bit at 0 5CH[1] Software reset SD1010D 5CH[0] Forces auto calibration to calculate the image quality for a particular clock phase (not used for sd1010d) 5DH[7] Turn on internal hsize matching by8, 4, 2 when clock frequency calibration is done by8, 4, 2. Used mainly for special non-full screen inputs. (not used) 5DH[6] 0: disable input video mode 1: input is video 5DH[5] 0: input video format is RGB 1: input video format is YUV 4:2:2 5DH[4] 0: input video YUV format is unsigned 1: input video YUV format is signed 5DH[3] Used when input resolution is higher than output 1: enable special decimation control 0: disable special decimation 5DH[2:1] Input data range detection. The results are put in register 64H and 65H 0: disable detection 1: detect MAX/MIN using R color 2: detect MAX/MIN using G color 3: detect MAX/MIN using B color 5DH[0] Automatic gain control enable 5EH Gain amount for R color 5FH Gain amount for G color 60H Gain amount for B color 61H Offset amount for R color 62H Offset amount for G color 63H Offset amount for B color 64H Detected maximum input data (please see 5DH) 65H Detected minimum input data (please see 5DH) 66H[5] Forces auto calibration to calculate the hsize value for a particular clock frequency (not used for sd1010d) 66H[4] Reset Man_hsize_valid register. (not used) 66H[3] 66H[2] 66H[1] 66H[0] 67H[2:0], 68H 69H[5:0], Reset Man_iq_valid register. (not used) Reset IQ_valid register. (not used) Reset Divisor_valid register (not used) Reset Non_full_screen register. Read only register containing value of clock frequency when divisor_valid is asserted Read only register containing value of image quality
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Panel_on
1
RW
6AH,6BH, when either man_iq_valid or iq_valid is asserted 6CH 6DH[0] 1: turn on all the outputs to the panel 0: disable outputs to the panel (need to disable EEPROM 265H[3], 266H[7], 266H[3], 267H[7], 267H[3] to get complete output disable). 6EH[2:0], 6FH 70H[7] 70H[6] Read only register containing value of hsize when man_hsize_valid is asserted. (not used in sd1010d) Move picture in left-right direction in digital mode 1: move picture to left 0: move picture to right Used mainly to compensate in the unlikely event when data and de are unalign coming into the SD1010D 70H[5:0] Divisor value use to divide fast pwm_free_clk to slower free_clk 71H Control Register F Bit[2:0]: Dithering Mode 0: compatible with SD1000 1-5: new schemes Bit[6:3]: reserved Bit[7]: gamma enable Default is 00H High water mark for valid data. If the data is larger than this threshold, it is considered High internally Low water mark for valid data. If the data is smaller than this threshold, it is considered LOW internally Minimum difference between the data value of two adjacent pixels to be considered as an edge.
Man_hsize_value Shift_hbp_digital Forward
11 1 1
R RW RW
Rom_clk_sel Control_F
6 8
RW RW
Data high threshold
8
RW
72H
Data low threshold
8
RW
73H
Edge threshold
8
RW
74H
Control Flow
When SD1010D is powered up, the reference system and SD1010D will perform the following functions in sequence: 1. System will generate a Power-On Reset to SD1010D. 2. Once the SD1010D receives the Reset, SD1010D will load the contents of EEPROM and start the auto-detection process. 3. In the meantime, the external CPU can change the contents of the control registers of the SD1010D. If necessary, the external CPU can send an additional Reset to restart the whole process.
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ELECTRICAL SPECIFICATIONS
This section presents the electrical specifications of the SD1010D.
Absolute Maximum Ratings
Symbol VCC Vin Vout VCC5 Vin5 Vout5 TSTG Parameter Power Supply Input Voltage Output Voltage Power Supply for 5V Input Voltage for 5V Output Voltage for 5V Storage Temperature Rating -0.3 to 3.6 -0.3 to VCC + 0.3 -0.3 to VCC +0.3 -0.3 to 6.0 -0.3 to VCC5 + 0.3 -0.3 to VCC5 +0.3 -55 to 150 Units V V V V V V C
Recommended Operating Conditions
Symbol VCC Vin VCC5 VIN5 TJ Parameter Power Supply Input Voltage Commercial Power Supply for 5V Input Voltage for 5V Commercial Junction Operating Temperature Min. 3.0 0 4.75 0 0 Typ. 3.3 5.0 25 Max. 3.6 VCC 5.25 VCC5 115 Units V V V V C
General DC Characteristics
Symbol IIL IOZ CIN3 COUT3 CBID3 CIN5 COUT5 CBID5 Parameter Input Leakage Current TRI-state Leakage Current 3.3V Input Capacitance 3.3V Output Capacitance 3.3V Bi-directional Buffer Capacitance 5V Input Capacitance 5V Output Capacitance 5V Bi-directional Buffer Capacitance Conditions no pull - up or pull - down Min. -1 -1 2.8 2.7 2.7 2.8 2.7 2.7 5.6 5.6 4.9 4.9 Typ. Max. 1 1 Units A A F F F F F F
Note: The capacitance above does not include PAD capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance, which is about 0.5 F, and the package capacitance
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DC Electrical Characteristics for 3.3 V Operation
(Under Recommended Operation Conditions and VCC = 3.0 ~ 3.6V, TJ = 0C to +115C)
Symbol VIL VIH VTParameter Input low voltage Input high voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up /down resistance Conditions CMOS CMOS COMS Min. 0.7*VCC 1.20 Typ. Max. 0.3*VCC Units V V V
VT+
COMS
2.10
V
VOL VOH RI
IOH=2,4,8,12, 16,24 mA IOH=2,4,8,12, 16,24 mA VIL=0V or VIH=VCC
0.4 2.4 75
V V K
DC Electrical Characteristics for 5V Operation
(Under Recommended Operation Conditions and VCC=4.75~5.25,TJ=0C to +115C)
Symbol VIL VIH VIL VIH VTVT+ Parameter Input low voltage Input high voltage Input low voltage Input high voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up / down resistance Conditions COMS Min. 0.7*VCC 0.8 2.0 1.78 3.00 Typ. Max. 0.3*VCC
COMS
TTL TTL CMOS COMS
Units V V V V V V
VTVT+
TTL TTL
1.10 1.90
V V
VOL VOH RI
IOL=2,4,8,16,24mA IOH=2,4,8,16,24 mA VIL=0V or VIH=VCC
0.4 3.5 50
V V K
525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
PACKAGE DIMENSIONS
128 60
1
102 20
12860 PQFP (1428x208 mm)
E
HE
384 0
648 0
D HD A A2 A1
c
b
e
L L1
525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
Symbol\Unit A A1 A2 b c D E e HD HE L L1
Inch (Base) 0.134(Max) 0.010 (Min) 0.112 +/-0.003 0.007 (Min) - 0.011(Max) .004 (Min) - 0.008 (Max) 0.551+/-0.002 0.787+/-0.002 0.020 (Ref) 0.677 +/- 0.01 0.913 +/- 0.01 0.035+/-0.006 0.063(Ref) 0 - 7.0
MM (Base) 3.40 (Max) 0.25 (Min) 2.85 +/- 0.08 0.17(Min) - 0.27(Max) 0.09(Min) - 0.20(Max) 14.000+/-0.10 20.000+/-0.10 0.5(Ref) 17.20 +/- 0.25 23.20 +/- 0.25 0.88+/-0.15 1.60(Ref) 0 - 7.0
525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
ORDER INFORMATION
Order Code SD1010
Temperature Package Speed Commercial 128-pin PQFP 100MHz 14 x 20 (mm) 0C ~ 70C
SmartASIC, Inc.
U.S.A. & Europe
WORLDWIDE OFFICES
Asia Pacific
525 Race St. Suite 250 San Jose, CA 95126 U.S.A. Tel : 1-408-283-5098 Fax : 1-408-283-5099
3F, No. 68, Chou-Tze St. Nei-Hu Dist. Taipei 114, Taiwan R.O.C. Tel : 886-2-8797-7889 Fax : 886-2-8797-6829
@Copyright 1999, SmartASIC, Inc.
This information in this document is subject to change without notice. SmartASIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. SmartASIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are
525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099
to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
525 Race Street, Suite 250, San Jose, CA 95126, USA. Main: (408) 283-5098 Fax: (408) 283-5099

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